The present invention relates to the field of programmable logic and devices therefor. More specifically, in one embodiment the invention provides an improved programmable logic device with that is especially useful in implementation of arithmetic functions, as well as associated methods of operation.
Programmable logic devices (PLDs) are well known to those in the electronics art. Such programmable logic devices are commonly referred to as PALs (Programmable Array Logic), PLAs (Programmable Logic Arrays), FPLAs (Field Programmable Logic Arrays), PLDs (Programmable Logic Devices), EPLDs (Erasable Programmable Logic Devices), EEPLDs, LCAs (Logic Cell Arrays), FPGAs (Field Programmable Gate Arrays), and the like. Such devices are used in a wide array of applications where it is desirable to program standard, off the shelf devices for a specific application. Such devices include, for example, the well known Classic.TM. EPLDs and MAX.RTM. 5000 EPLDs made by Altera.RTM..
While such devices have met with substantial success, such devices also meet with certain limitations. For example, when such devices are programmed to perform an addition function, such devices are not as efficient as could be hoped because carry operations use excessive resources when they are implemented on such devices. Specifically, according to one implementation of an add function in an EPLD, a single macrocell is used for each bit of the add, and an additional macrocell is needed for every third bit for carry generation. In addition, "expanders" are used for implementation of such add functions that provide "bit generate" and "bit propagate" signals, such as described in Langdon, Computer Design, 1982, pp. 494. Use of these resources not only reduces the capacity of the device to perform many functions, but also slows operation of the device.
From the above it is seen that an improved programmable logic device is desired.